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CX72300
Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
Conexant's CX72300 direct digital modulation fractional-N frequency synthesizer provides ultra-fine frequency resolution, fast switching speed, and low phase-noise performance. This synthesizer is a key building block for high-performance radio system designs that require low power and fine step size. The ultra-fine step size of less than 100 Hz allows this synthesizer to be used in very narrowband wireless applications. With proper temperature sensing or through control channels, the synthesizer's fine step size can compensate for crystal oscillator or Intermediate Frequency (IF) filter drift. As a result, crystal oscillators or crystals can replace temperature-compensated or ovenized crystal oscillators, reducing parts count and associated component cost. The CX72300's fine step size can also be used for Doppler shift corrections. The CX72300 has a phase noise floor of -90 dBc/Hz up to 2.1 GHz operation as measured inside the loop bandwidth. This is permitted by the on-chip low noise dividers and low divide ratios provided by the IC's high fractionality. Reference crystals or oscillators up to 50 MHz can be used with the CX72300. The crystal frequency is divided down by independent programmable divider ratios of 1 to 32 for the main and auxiliary synthesizers. The phase detectors can operate at a maximum speed of 25 MHz, which allows better phase noise due to the lower division value. With a high reference frequency, the loop bandwidths can also be increased. Larger loop bandwidths improve the settling times and reduce in-band phase noise. Therefore, typical switching times of less than 100 s can be achieved. The CX72300's lower in-band phase noise also permits the use of lower cost Voltage Controlled Oscillators (VCOs) in customer applications. The CX72300 has a frequency power steering circuit that helps the loop filter to steer the VCO when the frequency is too fast or too slow, further enhancing acquisition time. The unit operates with a three-wire, high-speed serial interface. A combination of large bandwidth, fine resolution, and the three-wire, high-speed serial interface allows for a direct frequency modulation of the VCO. This supports any continuous phase, constant envelope modulation scheme such as Frequency Modulation, Frequency Shift Keying, Minimum Shift Keying, or Gaussian Minimum Shift Keying (FM, FSK, MSK, GMSK). This capability can eliminate the need for Intermediate and Quadrature Digital-to-Analog Converters (I and Q DACs), quadrature upconverters, and IF filters from the transmitter portion of the radio system.
Distinguishing Features
* * * * * * * * * * * * * * * * * * * Spur-free operation 2.1 GHz maximum operating frequency 500 MHz maximum auxiliary synthesizer Ultra-fine step size, 100 Hz or less High internal reference frequency, up to 25 MHz, which enables a larger loop bandwidth Phase Locked Loop (PLL) Very fast switching speed (for example, below 100 s) Phase noise to -91 dBc/Hz inside the loop filter bandwidth @ 1800 MHz Software programmable power-down modes High-speed serial interface, up to 100 Mbps Three-wire programming Programmable division ratios on reference frequency Phase detectors with programmable gain, which provide a programmable loop bandwidth Frequency power steering further enhances rapid acquisition time On-chip crystal oscillator Frequency adjust for temperature compensation Direct digital modulation 3 V operation 5 V output to loop filter 28-pin Exposed Pad Thin Shrink Small Outline Package (EP-TSSOP)
Applications
* * * * * * General purpose RF systems 2.5G and 3G wireless infrastructure Broadband wireless access Low bit rate wireless telemetry Instrumentation L-band receivers
Data Sheet
101217P4 April 2002
Ordering Information
Model Number CX72300-11 Package 28-Pin Exposed Pad TSSOP Ambient Temperature Range -40 to +85 C Evaluation Kit Number PH00-D112
Revision History
Revision P2 P3 P4 Level Preliminary Date May 2001 October 2001 February 2002 Revised schematic Revised table. Revisions. Description
(c) 2001, 2002 Conexant Systems, Inc.
All Rights Reserved. Information in this document is provided in connection with Conexant Systems, Inc. ("Conexant") products. These materials are provided by Conexant as a service to its customers and may be used for informational purposes only. Conexant assumes no responsibility for errors or omissions in these materials. Conexant may make changes to specifications and product descriptions at any time, without notice. Conexant makes no commitment to update the information and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to its specifications and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Conexant's Terms and Conditions of Sale for such products, Conexant assumes no liability whatsoever. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF CONEXANT PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, CONSEQUENTIAL OR INCIDENTAL DAMAGES, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. CONEXANT FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. CONEXANT SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS. Conexant products are not intended for use in medical, lifesaving or life sustaining applications. Conexant customers using or selling Conexant products for use in such applications do so at their own risk and agree to fully indemnify Conexant for any damages resulting from such improper use or sale. The following are trademarks of Conexant Systems, Inc.: ConexantTM, the Conexant C symbol, and "What's Next in Communications Technologies"TM. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their respective owners. For additional disclaimer information, please consult Conexant's Legal Information posted at www.conexant.com, which is incorporated by reference. Reader Response: Conexant strives to produce quality documentation and welcomes your feedback. Please send comments and suggestions to tech.pubs@conexant.com. For technical questions, contact your local Conexant sales office or field applications engineer.
101217P4
Conexant
Functional Block Diagram
Data Clock CS Serial Interface Modul. Data Main Registers Main Div. Modul. Ctl Ref. Div. Synth Ctl Aux. Div. Aux.
Mod_in Modulation Unit Mux Mux_out
18-Bit
10-Bit
Fractional Unit
Fvco_main Fvco_main
Main Divider Main Divider Fpd_main Main Phase/Freq. Detector and Charge Pump
Reference Frequency Oscillator
Fractional Unit
Fvco_aux
Auxiliary Divider Fref_main Fref_aux Fref Reference Frequency Oscillator Fpd_aux Auxiliary Prescaler
Fvco_aux
Auxiliary Phase/Freq. Detector and Charge Pump
CPout_main
CPout_aux LD/PSaux
Lock Detection or Power Steering
LD/PSmain
Lock Detection or Power Steering
Conexant
101217P4
2
3
4
CX72300 Schematic Diagram
2 Mod_in Mux_out VSUBdigital GNDecl/cml VCCecl/cml Fvco_main Fvco_main LD/PSmain VCCcp_main CPout_main GNDcp_main Xtalacgnd/OSC GND Xtalin/OSC VCCcp_aux LD/PSaux GNDxtal VCCxtal Xtalout/NC CPout_aux 20 3V 10 2 C11 1 nF 11 12
A A
Data VCCdigital GNDdigital VCCecl/cml Fvco_aux Fvco_aux GNDcp_aux 21
A
27 3V 26 25 24 23 C4 C6
A A A
3 3V 4 5 C3 1 nF
A
C1 1 nF C2 1 nF
A
A
2
6
A
VCC VCC Auxiliary VCO 3
3
5
4
2
A
A
Lock Detect Main Output
A
R1 100 k 9 3V 19 18 17
RFOUT
VT
1
R4 R5 C14
A A
29
Conexant
3V C7 8
A
C8 R3
A
R2 C9
A
VCC
3
VCC
3V 16 15
C10 1 nF C12
A A
GND
A
4 14
13
Main VCO
Auxiliary Synthesizer Loop Filter C17 1 nF
A A
C15 C17
A
External Pad Connection to Ground
C16 100 pF Y1 C19 3V R6 100 k C18
Main Synthesizer Loop Filter
101217_016
Lock Detect Auxiliary Output
1
VT
Auxiliary VCO 4 GND
RFOUT
RF Out Main J1 1 C5 7 22
5
101217P4
To Microprocessor 3V RF Out Auxiliary J1 1 1 Clock CS 28
Table of Contents
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii 1.0 Technical Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Main and Auxiliary DS Modulators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Main and Auxiliary Fractional Units . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 VCO Prescalers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 Main and Auxiliary VCO Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Reference Frequency Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Reference Frequency Dividers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 Phase Detectors and Charge Pumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3
1.10 Frequency Steering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.11 Lock Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.12 Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
2.0
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1
2.1 2.2 Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Synthesizer Register Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2.1 2.2.2 Fractional-N Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.1.1 Fractional-N Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Integer-N Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2.1 Integer-N Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2.2.2 Register Loading Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2-3 2-3 2-6 2-6 2-7
2.3
Direct Digital Modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.3.1 2.3.2 2.3.3 Normal Register Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Short CS Through Data Pin (No Address Bits Required). . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 Short CS Through Mod_in Pin (No Address Bits Required) . . . . . . . . . . . . . . . . . . . . . . . 2-8
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Table of Contents
CX72300
Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
3.0
Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1
3.1 3.2 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1.1 3.2.1 3.2.2 3.2.3 Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 Main Synthesizer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Auxiliary Synthesizer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 General Synthesizer Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Synthesizer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2
4.0
Electrical/Mechanical. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1
4.1 4.2 4.3 4.4 4.5 Signal Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 Specifications and Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 Electrostatic Discharge Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Tape and Reel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
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CX72300
Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
List of Figures
List of Figures
Figure 1-1. Figure 2-1. Figure 3-1. Figure 3-2. Figure 3-3. Figure 3-4. Figure 3-5. Figure 3-6. Figure 3-7. Figure 3-8. Figure 3-9. Figure 3-10. Figure 4-1. Figure 4-2. CX72300 Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 Serial Transfer Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 Main Divider Register (Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 Main Dividend MSB Register (Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Main Dividend LSB Register (Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 Auxiliary Divider Register (Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Auxiliary Dividend Register (Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 Reference Frequency Dividers Register (Write Only). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-5 Control Register (Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 Power Down and Multiplexer Output Register (Write Only) . . . . . . . . . . . . . . . . . . . . . . . . 3-9 Modulation Control Register (Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 Modulation Data Register (Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 28-Pin EP-TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 Tape and Reel Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
List of Tables
Table 2-1. Table 3-1. Table 3-2. Table 3-3. Table 3-4. Table 4-1. Table 4-2. Table 4-3. Table 4-4. Table 4-5. Table 4-6. Table 4-7. Table 4-8. Table 4-9. CX72300-11 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CX72300 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming the Main Reference Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming the Auxiliary Reference Frequency Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . Multiplexer Output. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Reference Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VCOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Noise. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Phase Detectors and Charge Pumps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Digital Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timing--Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 3-1 3-5 3-5 3-7 4-1 4-1 4-2 4-2 4-2 4-3 4-3 4-3 4-4
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List of Tables
CX72300
Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
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1
1.0 Technical Description
The CX72300 is supplied as a 28-pin EP-TSSOP. The exposed pad is located on the bottom side of the package and must be connected to ground for proper operation. The exposed pad should be soldered directly to the circuit board. The device pinout is shown in Figure 1-1. The CX72300 is a fraction-N frequency synthesizer using a - modulation technique. The fractional-N implementation provides low in-band noise by having a low division ratio and fast frequency settling time. In addition, the CX72300 provides arbitrarily fine frequency resolution with a digital word, so that the frequency synthesizer can be used to compensate for crystal frequency drift in the RF transceiver.
Figure 1-1. CX72300 Pinout
Clock Mod_in Mux_out VSUBdigital GNDcml VCCcml_main Fvco_main Fvco_main LD/PSmain VCCcp_main CPout_main GNDcp_main Xtalacgnd/OSC Xtalin/OSC
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
CS Data VCCdigital GNDdigital VCCcml_aux Fvco_aux Fvco_aux GNDcp_aux CPout_aux VCCcp_aux LD/PSaux GNDxtal VCCxtal Xtalout/NC
101217_003
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1.0 Technical Description
1.1 Serial Interface
CX72300 Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
1.1 Serial Interface
The serial interface is a versatile three-wire interface, consisting of three pins: serial clock (Clock), serial input (Data), and chip select (CS). It enables the CX72300 to operate in a system with one or multiple masters and slaves. To perform a loopback test at startup and to check the integrity of the board and processor, the serial data is fed back to the master device (for example, a microcontroller or microprocessor unit) through a programmable multiplexer. This facilitates hardware and software debugging. For more information, see Section 2.1.
1.2 Registers
There are ten 16-bit registers in the CX72300. For more information, see Chapter 3.0.
1.3 Main and Auxiliary Modulators
The fractionality of the CX72300 is accomplished by the use of a proprietary, configurable 10-bit or 18-bit modulator for the main synthesizer and 10-bit modulator for the auxiliary synthesizer.
1.4 Main and Auxiliary Fractional Units
The CX72300 provides fractionality through the use of main and auxiliary modulators. The output from the main and auxiliary modulators is combined with the main and auxiliary divider ratios through their respective fractional units.
1.5 VCO Prescalers
The VCO prescalers provide low-noise signal conditioning of the VCO signals. They translate from an off-chip single-ended or differential signal to an on-chip differential Current Mode Logic (CML) signal. The CX72300 has independent main and auxiliary VCO prescalers.
1-2
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CX72300
Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
1.0 Technical Description
1.6 Main and Auxiliary VCO Dividers
1.6 Main and Auxiliary VCO Dividers
The CX72300 provides programmable dividers that control the CML prescalers and supply the required signals to the charge pump phase detectors. Programmable divide ratios ranging from 38 to 537 are possible in fractional-N mode and from 32 to 543 in integer-N mode.
1.7 Reference Frequency Oscillator
The CX72300 has a self-contained, low-noise crystal oscillator. This crystal oscillator is followed by the clock generation circuitry that generates the required clock for the programmable reference frequency dividers.
1.8 Reference Frequency Dividers
The crystal oscillator signal can be divided by a ratio of 1 to 32 to create the reference frequencies for the phase detectors. The CX72300 has both a main and an auxiliary frequency synthesizer, and provides independently configurable dividers of the crystal oscillator frequency for both the main and auxiliary phase detectors. The divide ratios are programmed through the Reference Frequency Dividers Register.
NOTE:
The divided crystal oscillator frequencies (which are the internal reference frequencies), Fref_main and Fref_aux, are referred to as the reference frequencies throughout this document.
1.9 Phase Detectors and Charge Pumps
The CX72300 uses a separate charge pump phase detector for each synthesizer which provides a programmable gain, Kd, from 31.25 through 1000 A/2 radians in 32 steps programmed via the Control Register.
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1.0 Technical Description
1.10 Frequency Steering
CX72300 Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
1.10 Frequency Steering
When programmed for frequency power steering, the CX72300 has a circuit that helps the loop filter steer the VCO, through the LD/PSmain pin. In this configuration, the LD/PSmain pin can provide for more rapid acquisition. When programmed for lock detection, internal frequency steering is implemented and provides frequency acquisition times comparable to conventional phase/frequency detectors.
1.11 Lock Detection
When programmed for lock detection, the CX72300 provides an active low, pulsing open collector output on the LD/PSmain pin to indicate the out-of-lock condition. When locked, the LD/PSmain pin is three-stated (high impedance).
1.12 Power Down
The CX72300 supports a number of power-down modes through the serial interface. For more information, see Section 3.2.3.
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2
2.0 Operation
This section describes the operation of the CX72300. The serial interface is described first, followed by information on how to obtain values for the Divide Ratio Registers.
2.1 Serial Interface
The serial interface consists of three pins: Clock, Data, and CS. The Clock signal controls data transfers that synchronize and sample the information on the two serial data lines (Data and CS). The data pin bits shift into a temporary register on the rising edge of Clock. The CS line allows individual selection of slave devices on the same bus. Figure 2-1 functionally depicts how a serial transfer takes place.
Figure 2-1. Serial Transfer Timing Diagram
Clock
Data
X
A3
A2
A1
A0 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
XXX
CS Last
101217_002
A serial transfer is initiated when a microcontroller or microprocessor forces the CS line to a low state. This is immediately followed by an address/data stream sent to the Data pin that coincides with the rising edges of the clock presented on the Clock line. Each rising edge of the Clock signal shifts in one bit of data on the Data line into a shift register. At the same time, one bit of data is shifted out of the Mux_out pin (if the serial bit stream is selected) at each falling edge of Clock. To load any of the synthesizer registers, 16 bits of address or data must be presented to the Data line with the data LSB last while CS is low. If CS is low for more than 16 clock cycles, only the last address or data bits are used to load the synthesizer registers. If the CS line is brought to a high state before the thirteenth clock edge on Clock, the bit stream is assumed to be modulation data samples. In this case, it is assumed that no address bits are present and that all the bits in the stream should be loaded into the Modulation Data Register.
101217P4
Conexant
2-1
2.0 Operation
2.2 Synthesizer Register Programming
CX72300 Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
2.2 Synthesizer Register Programming
Synthesizer register programming equations, described in this section, use the following variables and constants: Nfractional Desired VCO division ratio in fractional-N applications. This is a real number and can be interpreted as the reference frequency (Fref) multiplying factor such that the resulting frequency is equal to the desired VCO frequency. Desired VCO division ratio in integer-N applications. This number is an integer and can be interpreted as the reference frequency (Fref) multiplying factor such that the resulting frequency is equal to the desired VCO frequency. 9-bit unsigned input value to the divider ranging from 0 to 511 (integer-N mode) and from 6 to 505 (fractional-N mode) This constant equals 262144 when the modulator is in 18-bit mode, and 1024 when the modulator is in 10-bit mode When in 18-bit mode, this is the 18-bit signed input value to the modulator, ranging from -131072 to +131071 providing 262144 steps, each of Fdiv_ref / 218 (Hz). When in 10-bit mode, this is the 10-bit signed input value to the modulator, ranging from -512 to +511 providing 1024 steps, each of Fdiv_ref / 210 Hz. FVCO Fdiv_ref Desired VCO frequency (either Fvco_main or Fvco_aux). Divided reference frequency presented to the phase detector (either Fref_main or Fref_aux).
Ninteger
Nreg divider dividend
2-2
Conexant
101217P4
CX72300
Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
2.0 Operation
2.2 Synthesizer Register Programming
2.2.1 Fractional-N Applications
The desired division ratio for the main and auxiliary synthesizers is given by:
F VCO N fractional = ----------------F div_ref
where Nfractional must be between 37.5 and 537.5 for the auxiliary synthesizer. The value to be programmed in the Main or Auxiliary Divider Register is given by:
N reg = Round ( N fractional ) - 32
NOTE:
The Round function rounds the number to the nearest integer.
When in fractional mode, allowed values for Nreg are from 6 to 505 inclusive. The value to be programmed in the Main or Auxiliary Dividend Register is given by:
dividend = Round [ divider x ( N fractional - N reg - 32 ) ]
where the divider is either 1024 in 10-bit mode or 262144 in 18-bit mode. Therefore, the dividend is a signed binary value either 10 or 18 bits long.
NOTE:
Because of the high fractionality of the CX72300, there is no practical need for any integer relationship between the reference frequency and the channel spacing or desired VCO frequencies.
2.2.1.1 Fractional-N Example
Case 1:
To achieve a desired Fvco_main frequency of 902.4530 MHz using a crystal frequency of 40 MHz with operation of the synthesizer in 18-bit mode. Since the maximum internal reference frequency (Fdiv_ref) is 25 MHz, the crystal frequency is divided by 2 to obtain a Fdiv_ref of 20 MHz. Therefore:
F vco_main N fractional = ---------------------F div_ref 902.4530 = --------------------20 = 45.12265
101217P4
Conexant
2-3
2.0 Operation
2.2 Synthesizer Register Programming
CX72300 Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
The value to be programmed in the Main Divider Register is:
Nreg = Round [ N fractional ] - 32 = Round [ 45.12265 ] - 32 = 45 - 32 = 13 (decimal) = 000001101 (binary)
With the modulator in 18-bit mode, the value to be programmed in the Main Dividend Registers is:
dividend = Round [ divider x ( N fractional - N reg - 32 ) ] = Round [ 262144 x ( 45.12265 - 13 - 32 ) ] = Round [ 262144 x ( 0.12265 ) ] = Round [ 32151.9616 ] = 32152 (decimal) = 000111110110011000 (binary)
where 00 0111 1101 is loaded in the MSB of the Main Dividend Register and 1001 1000 is loaded in the LSB of the Main Dividend Register. Summary: * * * * *
NOTE:
Main Divider Register = 0 0000 1101 Main Dividend LSB Register = 1001 1000 Main Dividend MSB Register = 00 0111 1101 The resulting main VCO frequency is 902.453 Step size is 76.3 Hz The frequency step size for this case is 20 MHz divided by 218 giving 76.3 Hz.
2-4
Conexant
101217P4
CX72300
Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
Case 2:
2.0 Operation
2.2 Synthesizer Register Programming
Assuming a desired Fvco_main frequency of 917.7786 MHz and a crystal frequency of 19.2 MHz with operation of the synthesizer in 10-bit mode. Since the maximum internal reference frequency (Fdiv_ref) is 25 MHz, the crystal frequency does not require the internal division to be greater than 1, which makes Fdiv_ref = 19.2 MHz. Therefore:
F vco_main N fractional = ---------------------F div_ref 917.7786 = --------------------19.2 = 47.80097
The value to be programmed in the Main Divider Register is:
N reg = Round [ N fractional ] - 32 = Round [ 47.80139 ] - 32 = 48 - 32 = 16 (decimal) = 000010000 (binary)
With the modulator in 10-bit mode, the value to be programmed in the Main Dividend Registers is:
dividend = Round [ divider x ( N fractional - N reg - 32 ) ] = Round [ 1024 x ( 47.80139 - 16 - 32 ) ] = Round [ 1024 x ( - 0.19861 ) ] = Round [ - 203.38133 ] = - 203 (decimal) = 1100110101 (binary)
where 11 0011 0101 is loaded in the MSB of the Main Dividend Register. Summary: * * * *
NOTE:
Main Divider Register = 0 0001 0000 Main Dividend MSB Register = 11 0011 0101 The resulting VCO frequency is 917.7938 MHz Step size is 18.75 kHz The frequency step size for this case is 19.2 MHz divided by 210 giving 18.75 kHz.
101217P4
Conexant
2-5
2.0 Operation
2.2 Synthesizer Register Programming
CX72300 Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
2.2.2 Integer-N Applications
The desired division ratio for the main or auxiliary synthesizer is given by:
F vco_main N integer = ---------------------F div_ref
where Ninteger is an integer number from 32 to 543 for both the main and auxiliary synthesizers. The value to be programmed in the Main or Auxiliary Divider Register is given by:
N reg = N integer - 32
When in integer mode, allowed values for Nreg are from 0 to 511 for both the main and auxiliary synthesizers.
NOTE:
As with all integer-N synthesizers, the minimum step size is related to the crystal frequency and reference frequency division ratio.
2.2.2.1 Integer-N Example
Case 1:
To achieve a desired Fvco_aux frequency of 400 MHz using a crystal frequency of 16 MHz. Since the minimum divide ratio is 32, the reference frequency must be a maximum of 12.5 MHz. Choosing a reference frequency divide ratio of 2 provides a reference frequency (Fdiv_ref) of 8 MHz. Therefore:
F vco_aux N integer = ------------------F div_ref 400 = -------8 = 50
The value to be programmed in the Auxiliary Divider Register is:
N reg = N integer - 32 = 50 - 32 = 18 (decimal) = 000010010 (binary)
Summary: * Auxiliary Divider Register = 0 0001 0010
2-6
Conexant
101217P4
CX72300
Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
2.0 Operation
2.2 Synthesizer Register Programming
2.2.2.2 Register Loading Order
In applications where the main synthesizer is in 18-bit mode, the Main Dividend MSB Register holds the 10 MSBs of the dividend and the Main Dividend LSB Register holds the 8 LSBs of the dividend. The registers that control the main synthesizer's divide ratio are to be loaded in the following order: * * * Main Divider Register Main Dividend LSB Register Main Dividend MSB Register (at which point the new divide ratio takes effect)
In applications where the main synthesizer is in 10-bit mode, the Main Dividend MSB Register holds the 10 bits of the dividend. The registers that control the main synthesizer's divide ratio are to be loaded in the following order: * * Main Divider Register Main Dividend MSB Register (at which point the new divide ratio takes effect)
For the auxiliary synthesizer, the Auxiliary Dividend Register holds the 10 bits of the dividend. The registers that control the auxiliary synthesizer's divide ratio are to be loaded in the following order: * *
NOTE:
Auxiliary Divider Register Auxiliary Dividend Register (at which point the new divide ratio takes effect) When in integer mode, the new divide ratios take effect as soon as the Main or Auxiliary Divider Register is loaded.
101217P4
Conexant
2-7
2.0 Operation
2.3 Direct Digital Modulation
CX72300 Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
2.3 Direct Digital Modulation
The high fractionality and small step size of the CX72300 allow the user to tune to practically any frequency in the VCO's operating range. This frequency tuning allows direct digital modulation by programming the different desired frequencies at precise instants. Typically, the channel frequency is selected through the Main Divider and Dividend Register and the instantaneous frequency offset from the carrier is entered through the Modulation Data Register. The Modulation Data Register can be accessed in three ways, which are defined in the following subsections.
2.3.1 Normal Register Write
A normal 16-bit serial interface write occurs when CS is 16 clock cycles wide. The corresponding 16-bit modulation data is simultaneously presented to the Data pin. The content of the Modulation Data Register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (Fpd_main).
2.3.2 Short CS Through Data Pin (No Address Bits Required)
A shortened serial interface write occurs when CS is from 2 to 12 clock cycles wide. The corresponding modulation data (2 to 12 bits) is simultaneously presented to the Data pin. The Data pin is the default pin used to enter modulation data directly in the Modulation Data Register with shortened CS strobes. This method of data entry eliminates the register address overhead on the serial interface. All serial interface bits are re-synchronized internally at the reference oscillator frequency. The content of the Modulation Data Register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (Fpd_main).
2.3.3 Short CS Through Mod_in Pin (No Address Bits Required)
A shortened serial interface write occurs when CS is from 2 to 12 clock cycles wide. The corresponding modulation data (2 to 12 bits) is simultaneously presented on the Mod_in pin. The Mod_in pin is the alternate pin used to enter modulation data directly into the Modulation Data Register with shortened CS strobes. This mode is selected through the Modulation Control Register. This method of data entry also eliminates the register address overhead on the serial interface and allows a different device than the one controlling the channel selection to enter the modulation data (e.g., a microcontroller for channel selection and a digital signal processor for modulation data). All serial interface bits are re-synchronized internally at the reference oscillator frequency and the content of the Modulation Data Register is passed to the modulation unit at the next falling edge of the divided main VCO frequency (Fpd_main).
2-8
Conexant
101217P4
CX72300
Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
2.0 Operation
2.3 Direct Digital Modulation
Modulation data samples in the Modulation Data Register can be from 2 to 12 bits long, and enable the user to select how many distinct frequency steps are to be used for the desired modulation scheme. The user can also control the frequency deviation through the modulation data magnitude offset in the Modulation Control Register. This allows shifting of the modulation data to accomplish a 2m multiplication of frequency deviation. The programmable range of -0.5 to +0.5 of the main modulator can be exceeded up to the condition where the sum of the dividend and the modulation data conform to:
- 0.5625 ( N mod + dividend ) +0.5625
NOTE:
When the sum of the dividend and modulation data lie outside this range, the value of Ninteger must be changed. For a more detailed description of direct digital modulation functionality, refer to the Conexant document CX72300/1/2 Direct Digital Modulation Application Note, document number 101349.
101217P4
Conexant
2-9
2.0 Operation
2.3 Direct Digital Modulation
CX72300 Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
2-10
Conexant
101217P4
3
3.0 Registers
This section describes the CX72300 registers. All register writes are programmed address first, followed directly with data. MSBs are entered first. On power-up, all registers are reset to 0x000 except registers at addresses 0x0 and 0x3, which are set to 0x006.
3.1 Register Map
Table 3-1 provides a description for each of the CX72300 device registers.
Table 3-1. CX72300 Register Map Address (hexadecimal)
0 1 2 3 4 5 6 7 8 9 Main Divider Register Main Dividend MSB Register Main Dividend LSB Register Auxiliary Divider Register Auxiliary Dividend Register Reference Frequency Dividers Register Control Register--phase detector/charge pumps Control Register--power down/multiplexer output select Modulation Control Register Modulation Data Register Modulation Data Register(2)--direct input
Register(1)
Length Bits
12 12 12 12 12 12 12 12 12 12 2 length 12
Address Bits
4 4 4 4 4 4 4 4 4 4 0
NOTES:
(1) (2)
All registers are write only. No address bits are required for modulation data. Any serial data between 2 and 12 bits long is considered modulation data.
3.1.1 Register Descriptions
For more information on register loading order, see Section 2.2.2.2.
101217P4
Conexant
3-1
3.0 Registers
3.2 Synthesizer Registers
CX72300 Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
3.2 Synthesizer Registers
3.2.1 Main Synthesizer Registers
Figure 3-1. Main Divider Register (Write Only)
A3 0
A2 A1 0 0
A0 11 0 X
10 X
9
8
7
6
5
4
3
2
1
0
LSB
X MSB
Main Synthesizer Divider Index
101217_004
The Main Divider Register contains the integer portion closest to the desired fractional-N (or the integer-N) value minus 32 for the main synthesizer. This register, in conjunction with the Main Dividend Registers (which control the fraction offset from -0.5 to +0.5), allows selection of a precise frequency. As shown in Figure 3-1, the value to be loaded is: Main Synthesizer Divider Index = 9-bit value for the integer portion of the main synthesizer dividers. Valid values for this register are from 6 to 505 (fractional-N) or from 0 to 511 (integer-N). The Main Dividend MSB and LSB Registers control the fraction part of the desired fractional-N value and allow an offset of -0.5 to +0.5 to the main integer selected through the Main Divider Register. *
3-2
Conexant
101217P4
CX72300
Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
3.0 Registers
3.2 Synthesizer Registers
As shown in Figures 3-2 and 3-3, values to be loaded are: * * Main Synthesizer Dividend (MSBs) = 10-bit value for the MSBs of the 18-bit dividend for the main synthesizer. Main Synthesizer Dividend (LSBs) = 8-bit value for the LSBs of the 18-bit dividend for the main synthesizer.
The Main Dividend Register MSB and LSB values are 2's complement format.
NOTE:
When in 10-bit mode, the Main Synthesizer Dividend (LSBs) is not required.
For information on programming and loading order for these registers, see Chapter 2.0.
Figure 3-2. Main Dividend MSB Register (Write Only)
A3 0
A2 A1 0 0
A0 11 1 X
10
9
8
7
6
5
4
3
2
1
0
LSB
X MSB
Main Synthesizer Dividend (MSBs)
101217_005
Figure 3-3. Main Dividend LSB Register (Write Only)
A3 0 A2 A1 0 1 A0 11 0 X 10 X 9 X 8 7 6 5 4 3 2 1 0
LSB
X MSB
Main Synthesizer Dividend (LSBs)
101217_006
101217P4
Conexant
3-3
3.0 Registers
3.2 Synthesizer Registers
CX72300 Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
3.2.2 Auxiliary Synthesizer Registers
The Auxiliary Divider Register contains the integer portion closest to the desired fractional-N (or integer-N) value minus 32 for the auxiliary synthesizer. This register, in conjunction with the Auxiliary Dividend Register, which controls the fraction offset (from -0.5 to +0.5), allows selection of a precise frequency. As shown in Figure 3-4, the value to be loaded is: * Auxiliary Synthesizer Divider Index = 9-bit value for the integer portion of the auxiliary synthesizer dividers. Valid values for this register are from 6 to 505 (fractional-N) or from 0 to 511 (integer-N).
The Auxiliary Dividend Register controls the fraction part of the desired fractional-N value and allows an offset of -0.5 to +0.5 to the auxiliary integer selected through the Auxiliary Divider Register. As shown in Figure 3-5, the value to be loaded is: * Auxiliary Synthesizer Dividend = 10-bit value for the dividend for the auxiliary synthesizer.
For information on programming and loading order for these registers, see Chapter 2.0.
Figure 3-4. Auxiliary Divider Register (Write Only)
A3 0
A2 A1 0 1
A0 11 1 X
10 X
9
8
7
6
5
4
3
2
1
0
LSB
X MSB
Auxiliary Synthesizer Divider Index
101217_007
Figure 3-5. Auxiliary Dividend Register (Write Only)
A3 0
A2 A1 1 0
A0 11 0 X
10
9
8
7
6
5
4
3
2
1
0
LSB
X MSB
Auxiliary Synthesizer Dividend
101217_008
3-4
Conexant
101217P4
CX72300
Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
3.0 Registers
3.2 Synthesizer Registers
3.2.3 General Synthesizer Registers
Figure 3-6. Reference Frequency Dividers Register (Write Only)
A3 0 A2 A1 1 0 A0 11 1 X 10 X 9 8 7 6 5 4 3 2 1 0
Main Reference Frequency Divider Index
Auxiliary Reference Frequency Divider Index
101217_009
The Reference Frequency Dividers Register configures the dual-programmable reference frequency dividers for the main and auxiliary synthesizers. The dual-programmable reference frequency dividers provide the reference frequencies to the phase detectors by dividing the crystal oscillator frequency. The lower five bits hold the reference frequency divide index for the main phase detector. The next five bits hold the reference frequency divide index for the auxiliary phase detector. Divide ratios from 1 to 32 are possible for each reference frequency divider. As shown in Figure 3-6, the values to be loaded are: * Main Reference Frequency Divider Index = Desired main oscillator frequency division ratio -1. Default value on power-up is 0, signifying that the reference frequency is not divided for the main phase detector. See Table 3-2 for other programming values. Auxiliary Reference Frequency Divider Index = Desired auxiliary oscillator frequency division ratio -1. Default value on power-up is 0, signifying that the reference frequency is not divided for the auxiliary phase detector. See Table 3-3 for other programming values.
*
101217P4
Conexant
3-5
3.0 Registers
3.2 Synthesizer Registers
CX72300 Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
Table 3-2. Programming the Main Reference Frequency Divider Decimal
0 1 2 -- -- -- 31
Bit 4 (MSB)
0 0 0 -- -- -- 1
Bit 3
0 0 0 -- -- -- 1
Bit 2
0 0 0 -- -- -- 1
Bit 1
0 0 1 -- -- -- 1
Bit 0 (LSB)
0 1 0 -- -- -- 1
Reference Divider Ratio
1 2 3 -- -- -- 32
Table 3-3. Programming the Auxiliary Reference Frequency Divider Decimal
0 1 2 -- -- -- 31
Bit 9 (MSB)
0 0 0 -- -- -- 1
Bit 8
0 0 0 -- -- -- 1
Bit 7
0 0 0 -- -- -- 1
Bit 6
0 0 1 -- -- -- 1
Bit 5 (LSB)
0 1 0 -- -- -- 1
Reference Divider Ratio
1 2 3 -- -- -- 32
3-6
Conexant
101217P4
CX72300
Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
3.0 Registers
3.2 Synthesizer Registers
The Control Register allows control of the gain for both phase detectors and configuration of the LD/PSmain and LD/PSaux pins for frequency power steering or lock detection. As shown in Figure 3-7, the values to be loaded are: * Main Phase Detector Gain = 5-bit value for programmable main phase detector gain. Range is from 0 to 31 decimal for 31.25 to 1000 A/ 2 radian, respectively. Main Power Steering Enable = 1-bit value to enable the frequency power steering circuitry of the main phase detector. When this bit is a 0, the LD/PSmain pin is configured to be a lock detect, active low, open collector pin. When this bit is a 1, the LD/PSmain pin is configured to be a frequency power steering pin and can be used to bypass the external main loop filter to provide faster frequency acquisition. Auxiliary Phase Detector Gain = 5-bit value for programmable auxiliary phase detector gain. Range is from 0 to 31 decimal for 31.25 to 1000 A/radian, respectively. Auxiliary Power Steering Enable = 1-bit value to enable the frequency power steering circuitry of the auxiliary phase detector. When this bit is a 0, the LD/PSaux pin is configured to be a lock detect, active low, open collector pin. When this bit is a 1, the LD/PSaux is configured to be a frequency power steering pin and may be used to bypass the external auxiliary loop filter to provide faster frequency acquisition.
*
*
*
Figure 3-7. Control Register (Write Only)
A3 0
A2 A1 1 1
A0 11 0
10
9
8
7
6
5
4
3
2
1
0
Main Phase Detector Gain Main Power Steering/Lock Detect Enable Auxiliary Phase Detector Gain Auxiliary Power Steering/Lock Detect Enable
101217_010
101217P4
Conexant
3-7
3.0 Registers
3.2 Synthesizer Registers
CX72300 Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
The Power Down and Multiplexer Output Register allows control of the power-down modes, internal multiplexer output, and main synthesizer fractionality. As shown in Figure 3-8, the values to be loaded are: * Full Power Down = 1-bit value that powers down the CX72300 except for the reference oscillator and the serial interface. When this bit is 0, the CX72300 is powered up. When this bit is 1, the CX72300 is in full power-down mode excluding the Mux_out pin. Main Synthesizer Power Down = 1-bit value that powers down the main synthesizer. When this bit is 0, the main synthesizer is powered up. When this bit is 1, the main synthesizer is in power-down mode. Main Synthesizer Mode = 1-bit value that powers down the main synthesizer's modulator and fractional unit to operate as an integer-N synthesizer. When this bit is 0, the main synthesizer is in fractional-N mode. When this bit is 1, the main synthesizer is in integer-N mode. Main Synthesizer Fractionality = 1-bit value that configures the size of the main modulator. This has a direct effect on power consumption and on the level of fractionality and step size. When this bit is 0, the main modulator is 18-bit with a fractionality of 218 and a step size of Fref_main/262144. When this bit is 1, the main modulator is 10-bit with a fractionality of 210 and a step size of Fref_main/1024. Auxiliary Synthesizer Power Down = 1-bit value that powers down the auxiliary synthesizer. When this bit is 0, the auxiliary synthesizer is powered up. When this bit is 1, the auxiliary synthesizer is in power-down mode. Auxiliary Synthesizer Mode = 1-bit value that powers down the auxiliary synthesizer's modulator and fractional unit to operate as an integer-N synthesizer. When this bit is 0, the auxiliary synthesizer is in fractional-N mode. When this bit is 1, the auxiliary synthesizer is in integer-N mode. There are no special power-up sequences required for the CX72300. Multiplexer Output Selection = 3-bit value that selects which internal signal is output to the Mux_out pin. The following internal signals are available on this pin: - Reference Oscillator: Fref - Main or auxiliary divided reference (post reference frequency main or auxiliary dividers): Fref_main or Fref_aux - Main or auxiliary phase detector frequency (post main and auxiliary frequency dividers): Fpd_main or Fpd_aux - Serial data out for loop-back and test purposes Mux_out Pin Three-State Enable = 1-bit value to three-state the Mux_out pin. When this bit is 0, the Mux_out pin is enabled. When this bit is 1, the Mux_out pin is three-stated.
*
*
*
*
*
NOTE:
*
*
Refer to Table 3-4 for more information.
3-8
Conexant
101217P4
CX72300
Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
3.0 Registers
3.2 Synthesizer Registers
Figure 3-8. Power Down and Multiplexer Output Register (Write Only)
A3 0
A2 A1 1 1
A0 11 1 X
10 X
9
8
MSB
7
6
LSB
5
4
3
2
1
0
Full Power Down Main Synthesizer Power Down Main Synthesizer Mode Main Synthesizer Fractionality Auxiliary Synthesizer Power Down Auxiliary Synthesizer Mode Multiplexer Output Selection Mux_out Pin Three-State Enable
101217_011
Table 3-4. Multiplexer Output Multiplexer Output Select bit 8
0 0 0 0 1 1 1
Multiplexer Output Select bit 7
0 0 1 1 0 0 1
Multiplexer Output Select bit 6
0 1 0 1 0 1 0 Reference Oscillator
Multiplexer Output (Mux_out)
Auxiliary Reference Frequency (Fref_aux) Main Reference Frequency (Fref_main) Auxiliary Phase Detector Frequency (Fpd_aux) Main Phase Detector Frequency (Fpd_main) Serial data out Serial Interface Register test output
The Modulation Control Register is used to configure the modulation unit of the main synthesizer. The modulation unit adds or subtracts a frequency offset to the selected center frequency at which the main synthesizer operates. The size of the modulation data sample, controlled by the duration of the CS pin, can be from 2 to 12 bits wide, to provide from 4 to 4096 selectable frequency offset steps. The modulation data magnitude offset selects the magnitude multiplier for the modulation data and can be from 0 to 8.
101217P4
Conexant
3-9
3.0 Registers
3.2 Synthesizer Registers
CX72300 Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
As shown in Figure 3-9, the values to be loaded are: * Modulation Data Magnitude Offset = 4-bit value that indicates the magnitude multiplier (m) for the modulation data samples. Valid values range from 0 to 13, effectively providing a 2m multiplication of the modulation data sample. Modulation Data Input Select = 1-bit value that indicates the pin on which modulation data samples are serially input when the CS signal is between 2 and 12 bits long. When this bit is 0, modulation data samples are to be presented on the Data pin. When this bit is 1, modulation data samples are to be presented on the Mod_in pin. For more details, refer to Section 2.3. Modulation Address Disable = 1-bit value that indicates the presence of the address as modulation data samples are presented on either the Mod_in or Data pins. When this bit is 0, the address is presented with the modulation data samples (i.e., all transfers are 16 bits long). When this bit is 1, no address is presented with the modulation data samples (i.e., all transfers are 2 to 12 bits long). For more details, refer to Section 2.3.
*
*
Figure 3-9. Modulation Control Register (Write Only)
A3 1
A2 A1 0 0
A0 11 0 X
10 X
9
8
7
6
5
4
3 0
2 0
1 0
0 0
Reserved Bits Modulation Data Magnitude Offset Modulation Data Input Select Modulation Address Disable
101217_012
The Modulation Data Register loads the modulation data samples to the modulation unit. This value is transferred to the modulation unit on the falling edge of Fpd_main where it is passed to the main modulator at the selected magnitude offset on the next falling edge of Fpd_main. Modulation Data Register values are 2's complement format. As shown in Figure 3-10, the value to be loaded is: * Modulation Data Bits = Modulation data samples that represent the instantaneous frequency offset to the selected main synthesizer frequency (selected channel) before being affected by the modulation data magnitude offset.
3-10
Conexant
101217P4
CX72300
Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
3.0 Registers
3.2 Synthesizer Registers
Figure 3-10. Modulation Data Register (Write Only)
A3 1
A2 A1 0 0
A0 11 1 MSB
10
9
8
7
6
5
4
3
2
1
0
LSB
Modulation Data Bits
101217_013
101217P4
Conexant
3-11
3.0 Registers
3.2 Synthesizer Registers
CX72300 Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
3-12
Conexant
101217P4
4
4.0 Electrical/Mechanical
4.1 Signal Pin Assignments
Signal pin assignments and functional pin descriptions are specified in Table 4-1.
Table 4-1. CX72300 Pin Description (1 of 2) Pin Label
Clock 1
Pin #
Type
Digital input
Description
Clock signal pin. When CS is low, the register address and data is shifted in address bits first on the Data pin on the rising edge of Clock. For more information, see Section 2.1. Serial address and data input pin. Address bits are followed by data bits. For more information, see Section 2.1. Active low enable pin. Enables loading of address and data on the Data pin on the rising edge of Clock. When CS goes high, data is transferred to the register indicated by the address. Subsequent clock edges are ignored. For more information, see Section 2.1. Alternate serial modulation data input pin. Address bits are followed by data bits. Internal multiplexer output. Selects from oscillator frequency, main or auxiliary reference frequency, main or auxiliary divided VCO frequency, serial data out or testability signals. This pin can be three-stated from the general synthesizer registers. For more information, see Section 3.2.3. Reference crystal AC ground, or external oscillator complementary input. Reference crystal input, or external oscillator differential input. Reference crystal output, or no connect. Main VCO differential input. Main VCO complimentary differential input. Auxiliary VCO differential input. Auxiliary VCO complimentary differential input. Main charge pump output. The gain of the main charge pump phase detector can be controlled from the general synthesizer registers.
Data CS
27 28
Digital input Digital input
Mod_in Mux_out
2 3
Digital input Digital output
Xtalacgnd/OSC Xtalin/OSC Xtalout/NC Fvco_main Fvco_main Fvco_aux Fvco_aux CPout_main
13 14 15 7 8 23 22 11
Ground/Input Input Input Input Input Input Input Analog output
101217P4
Conexant
4-1
4.0 Electrical/Mechanical
4.1 Signal Pin Assignments
CX72300 Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
Table 4-1. CX72300 Pin Description (2 of 2) Pin Label
LD/PSmain 9
Pin #
Type
Analog output
Description
Programmable output pin. Indicates main phase detector out-of-lock as an active low pulsing open collector output (high impedance when lock is detected), or helps the loop filter steer the main VCO. This pin is configured from the general synthesizer registers. Auxiliary charge pump output. The gain of the auxiliary charge pump phase detector can be controlled from the general synthesizer registers. Programmable output pin. Indicates auxiliary phase detector out-of-lock as an active low pulsing open collector output (high impedance when lock is detected), or helps the loop filter steer the auxiliary VCO. This pin is configured from the general synthesizer registers. Digital 3 V. Digital ground. Crystal oscillator Emitter Coupled Logic (ECL)/Current Mode Logic (CML) 3 V. Crystal oscillator ground. ECL/CML 3 V. Removing power safely powers down the associated divider chain and charge pump. ECL/CML ground. Main and auxiliary charge pump 3 to 5 V. Removing power safely powers down the associated divider chain and charge pump. Main and auxiliary charge pump ground.
CPout_aux LD/PSaux
20 18
Analog output Analog output
VCCdigital(1) GNDdigital(1) VCCxtal GNDxtal VCCcml/main(1) VCCcml_aux(1) GNDecl/cml(1) VCCcp_main(1) VCCcp_aux(1) GNDcp_main(1) GNDcp_aux(1) VSUBdigital
NOTE:
(1)
26 25 16 17 6 24 5 10 19 12 21 4
Power and ground Power and ground Power and ground Power and ground Power and ground Power and ground Power and ground Power and ground --
Substrate isolation, connect to ground.
Associated pairs of power and ground pins must be decoupled using 0.1 F capacitors.
4-2
Conexant
101217P4
CX72300
Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
4.0 Electrical/Mechanical
4.2 Specifications and Ratings
4.2 Specifications and Ratings
Table 4-2. Absolute Maximum Ratings Parameter
Maximum analog RF supply voltage Maximum digital supply voltage Maximum charge pump supply voltage Storage temperature Operating temperature 3.6 VDC 3.6 VDC 5.25 VDC -65 C to +150
Rating
C
-40 C to +85 C
Table 4-3. Recommended Operating Conditions Parameter
Analog RF supplies Digital supply Charge pump supplies Operating temperature (TA) +2.7 to +3.3 VDC +2.7 to +3.3 VDC +2.7 to +5.0 VDC -40 C to +85 C
Rating
Table 4-4. Power Consumption Symbol
Ptotal
Parameter
Total power consumption
Conditions
Charge pump currents of 200 A Both synthesizers fractional Fref_main = 20 MHz Fref_aux = 1 MHz Auxiliary synthesizer power-down
Min.
--
Typ.
37.5
Max.
--
Units
mW
-- --
27 10
-- -- A
--
ICC-PWDN
Power-down current
--
101217P4
Conexant
4-3
4.0 Electrical/Mechanical
4.2 Specifications and Ratings
CX72300 Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
Table 4-5. Reference Oscillator Symbol
Fosc Vosc Fshift_supply
Parameter
Reference oscillator frequency Oscillator sensitivity (as a buffer) Frequency shift versus supply voltage
Conditions
-- AC coupled, single-ended T = 25C 2.7 V Vxtal 3.3 V
Min.
-- 0.1 --
Typ.
-- -- --
Max.
50 2.0 0.3
Units
MHz Vpp ppm
Table 4-6. VCOs Symbol
Fvco_main Fvco_aux Vvco Zvco_in
Parameter
Main synthesizer operating frequency Auxiliary synthesizer operating frequency RF input sensitivity RF input impedance
Conditions
Min.
100(1)
Typ.
-- -- -- 94 - j140 @ 1200 MHz
Max.
2100 500 250 --
Units
Sinusoidal
100(1) 50
MHz
AC Coupled --
mVpeak
Fstep_main Fstep_aux
NOTE:
(1)
Main fractional-N tuning step size Auxiliary fractional-N tuning step size
-- --
Fref_main / 218 or Fref_main / 210 Hz Fref_aux / 210
When operating in fractional mode, minimum synthesizer frequency is 12x Fosc, where Fosc is the frequency at the Xtalin/OSC pin.
Table 4-7. Noise Symbol
PNF
Parameter
Phase noise floor
Conditions
Measured inside the loop bandwidth using 25 MHz reference frequency.
Min.
--
Typ.
-128 + 20 Log(N)
Max.
--
Units
dBc/Hz
4-4
Conexant
101217P4
CX72300
Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
4.0 Electrical/Mechanical
4.2 Specifications and Ratings
Table 4-8. Phase Detectors and Charge Pumps Symbol
Fref_main Fref_aux Icp-source Icp-sink Icp-accuracy Icp vs. Vcp Icp vs. T Icp vs. Vcp
Parameter
Main phase detector frequency Auxiliary phase detector frequency Charge pump output source current Charge pump output sink current -- Charge pump output voltage linearity range Charge pump current versus temperature Charge pump current versus voltage
Conditions
Min.
--
Typ.
--
Max.
25
Units
MHz
125 Vcp = 0.5 VCCcp -125 -- 0.5 V Vcp (VCCcp -0.5 V) T = 25C Vcp = 0.5 VCCcp -40 C < T < +85 C 0.5 V Vcp (VCCcp -0.5 V) T = 25 C -- Gnd + 400 -- --
-- --
1000 -1000 -- VCCcp - 400 5 % 8 A
20
-- -- --
% mV
Table 4-9. Digital Pins Symbol
VIH VIL VOH VOL
Parameter
High level input voltage Low level input voltage High level output voltage Low level output voltage
Conditions
-- -- IOH = -2 mA IOL = 2 mA
Min.
0.7 Vdigital -- Vdigital - 0.2 --
Typ.
-- -- -- --
Max.
-- 0.3 Vdigital -- Gnd + 0.2 V
Units
Table 4-10. Timing--Serial Interface Symbol
fclock tsu thold
Parameter
Clock frequency Data and CS set up time to Clock rising Data and CS hold time after Clock rising
Conditions
-- -- -- 3 0
Min.
--
Typ.
-- -- --
Max.
100 -- --
Units
MHz ns ns
101217P4
Conexant
4-5
4.0 Electrical/Mechanical
4.3 Electrostatic Discharge Information
CX72300 Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
4.3 Electrostatic Discharge Information
The CX72300 device is an electrostatic sensitive device. Observe precautions when handling.
4.4 Package Information
Figure 4-1. 28-Pin EP-TSSOP
b e 1
E E1 P1
D TOP VIEW
P EXPOSED PAD BOTTOM VIEW
Millimeters Dim. MIN. A A A1 A2 A1 A2 D E L SIDE VIEW DETAIL E1 L P P1 e b 0.05 0.85 MAX. 1.10 0.15 0.95
9.70 BSC 6.40 BSC 4.30 0.50 4.50 0.70 3.50 3.00 0.65 BSC 0.19 0.30
101217_014
4-6
Conexant
101217P4
CX72300
Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
4.0 Electrical/Mechanical
4.5 Tape and Reel
4.5 Tape and Reel
Figure 4-2. Tape and Reel Drawing
1.50 0.10 8.00 0.10 Pin #1 indicator 4.00 0.10
1.75 0.10 2.00 0.05
7.50 0.10
16.00 +0.30/-0.10
1.50 0.25 3.96 1.10 0.318 0.013
8o Max 6.75 0.10 1.60 0.10 9.95 0.10
7o Max
NOTE(S): 1. Carrier tape material: black conductive polycarbonate 2. Cover tape material: transparent conductive PSA 3. Cover tape size: 13.3 mm width 4. Tolerance: .XX = 0.10 5. All measurements are in millimeters
101217_017
101217P4
Conexant
4-7
4.0 Electrical/Mechanical
4.5 Tape and Reel
CX72300 Spur-Free, 2.1 GHz Dual Fractional-N Frequency Synthesizer
4-8
Conexant
101217P4
www.conexant.com General Information: U.S. and Canada: (800) 854-8099 International: (949) 483-6996 Headquarters - Newport Beach 4311 Jamboree Rd. Newport Beach, CA. 92660-3007

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